Method for forming spacers of a transistor
US11393689B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 10, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Aug 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming spacers on a gate pattern includes deposition of a first dielectric layer having basal portions on an active layer and side portions of the edges of the pattern; anisotropic modification of only the basal portions of the first layer, so as to obtain modified basal portions; deposition of a second dielectric layer on the first layer, also having basal and side portions; anisotropic etching of only the basal portions of the second layer, so as to remove these basal portions while conserving the side portions; and removal of the modified basal portions while conserving the first and second non-modified side portions, by selective etching of the modified dielectric material vis-à-vis the non-modified dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.