Alignment structure for semiconductor device and method of forming same
US11393769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | May 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.