Integrated circuit package with glass spacer
US11393788B2 · kind B2 · utility
0Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2016 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Apr 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.