Patent · US Active

Memory with TSV health monitor circuitry

US11393790B2 · kind B2 · utility

3Cited by
0References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 6, 2019
Grant dateJul 19, 2022
Priority date
Expiry dateFeb 10, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/15311
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.