Ultra-low profile stacked RDL semiconductor package
US11393808B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 2, 2019 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Nov 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.