RF DAC with improved HD2 and cross-talk performance by shadow switching in bleeder path
US11394393B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Jan 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DAC cell includes first and second transistors, drain-source coupled at a first node, a gate of the second transistor coupled to a data input (D), and third and fourth transistors, drain-source coupled at a second node, a gate of the fourth transistor coupled to a complement of the data input (DB). The circuit further includes first and second shadow transistors each coupled between the first node and ground, a gate of the first shadow transistor coupled to a switching input (S) and a gate of the second shadow transistor coupled to a complement of the switching input (SB). The circuit still further includes third and fourth shadow transistors each coupled between the second node and ground, a gate of the third shadow transistor coupled to S and a gate of the fourth shadow transistor coupled to SB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.