Wafer-level passive array packaging
US11395408B2 · kind B2 · utility
1Cited by
12References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Aug 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/1053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Wafer level passive array packages and modules are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.