Asynchronous communication protocol compatible with synchronous DDR protocol
US11397698B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2020 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Jan 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.