Semiconductor memory device
US11398286B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2021 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Mar 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array and peripheral circuitry. The memory cell array includes a block of memory cells The peripheral circuitry can perform first program-verify loops in response to a first write operation to a first word line in a word line group to program memory cells associated with the first word line to multiple states. The word line group includes one or more word lines. Then, the peripheral circuitry determines verification start loops of the multiple states based on sensing results in the first program-verify loops, and performs second program-verify loops with the determined verification start loops of the multiple states in response to a second write operation to a second word line in the word line group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.