Stacked memory device and memory system including the same
US11398290B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2020 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Jan 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06596
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including a data pad, and first and second data strobe pads, a data strobe signal generation circuit suitable for generating a read data strobe signal, outputting the read data strobe signal to the first data strobe pad, and generating an internal data strobe signal based on the read data strobe signal, during a test read operation, an input circuit suitable for feeding back and receiving data outputted to the data pad, during the test read operation, an alignment circuit suitable for aligning data received by the input circuit, based on the internal data strobe signal, and a test register circuit suitable for performing a preset operation on the data aligned by the alignment circuit and storing data obtained through the preset operation, wherein the test register circuit outputs the stored data to a read path during the test read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.