Selective deposition of metal barrier in damascene processes
US11398406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2018 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Dec 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.