Edge interconnect self-assembly substrate
US11398463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2020 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Feb 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a quilt package nodule includes forming a trench in a microchip substrate, forming a metal layer on the bottom, the first and second sides of the trench, and on a top surface of the microchip substrate proximate the first and second sides. forming a mask layer on the metal layer, removing portions of the mask and metal layers on the bottom of the trench, etching the bottom of the trench to increase the depth of the bottom of the trench, removing remaining portions of the mask layer from the metal layer to define the quilt package nodules that protrude beyond edges of the first and second sides, and removing the remaining portion of the trench bottom thereby separating the first and second sides from each other, whereupon each side includes at least one quilt package nodule protruding from the side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.