Methods for forming integrated circuit having guard rings
US11398467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2020 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Nov 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/307
Abstract
A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.