Electrostatic discharge (ESD) protection in stacked chips
US11398469B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2020 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Dec 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Examples described herein generally relate to devices that include electrostatic discharge (ESD) protection in a chip stack. In an example, a device includes a chip stack including first and second chips, ground and power supply voltage nodes, and first and second resistor-capacitor (RC) clamps. The second chip is disposed on and attached to the first chip. The ground and power supply voltage nodes are connected between and extend in the first and second chips, and are connected to the ground and power supply voltage exterior connector pads, respectively, of the first chip. The first and second RC clamps are disposed in the first and second chips, respectively. The first and second RC clamps are connected to and between the ground node and the power supply voltage node. An RC-time constant of the second RC clamp is less than an RC-time constant of the first RC clamp.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.