Vertical thing-film transistor and application as bit-line connector for 3-dimensional memory arrays
US11398492B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2020 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Feb 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6743
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer, and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.