Method for producing an electronic component with double quantum dots
US11398593B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2018 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Oct 17, 2038 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y40/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A process for fabricating an electronic component incorporating double quantum dots and split gates includes providing a substrate surmounted with a stack of a semiconductor layer and of a dielectric layer that is formed above the semiconductor layer. The process also includes forming a mask on the dielectric layer and etching the dielectric layer and the semiconductor layer with the pattern of the mask, so as to form a stack of a semiconductor nanowire and of a dielectric hard mask. Finally, the process includes depositing a gate material on all of the wafer and carrying out a planarization, until the dielectric hard mask is reached, so as to form first and second gates that are electrically insulated from each other on either side of said nanowire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.