Inventor · Voiron, FR

Maud Vinet

90Patents
7h-index
69Co-inventors
71Inventor score

Filing activity: Dec 16, 2003 → Apr 11, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8183630B2 Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT Electricity 252 Active
US8013399B2 SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable Electricity 228 Active
US8853785B2 Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit Electricity 179 Active
US8969148B2 Method for producing a transistor structure with superimposed nanowires and with a surrounding gate Emerging Cross-Sectional Technologies 15 Active
US8116118B2 Memory cell provided with dual-gate transistors, with independent asymmetric gates Electricity 10 Active
US7829916B2 Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor Electricity 10 Active
US9105691B2 Contact isolation scheme for thin buried oxide substrate devices Electricity 9 Active
US9252208B1 Uniaxially-strained FD-SOI finFET Electricity 7 Active
US9570465B2 Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same Electricity 6 Active
US8703550B2 Dual shallow trench isolation liner for preventing electrical shorts Electricity 6 Active
US7973350B2 Strained-channel transistor device Electricity 6 Active
US7968945B2 Microelectronic device provided with transistors coated with a piezoelectric layer Electricity 6 Active
US9171757B2 Dual shallow trench isolation liner for preventing electrical shorts Electricity 6 Active
US10468436B2 Method of manufacturing a LED matrix display device Electricity 5 Active
US9570340B2 Method of etching a crystalline semiconductor material by ion implantation and then chemical etching based on hydrogen chloride Electricity 4 Active
US9634103B2 CMOS in situ doped flow with independently tunable spacer thickness Electricity 4 Active
US9876121B2 Method for making a transistor in a stack of superimposed semiconductor layers Electricity 4 Active
US9601511B2 Low leakage dual STI integrated circuit including FDSOI transistors Electricity 4 Active
US8890219B2 UTBB CMOS imager having a diode junction in a photosensitive area thereof Electricity 3 Active
US7812410B2 Suspended-gate MOS transistor with non-volatile operation Electricity 3 Active
US7768821B2 Non-volatile SRAM memory cell equipped with mobile gate transistors and piezoelectric operation Physics 3 Active
US8399316B2 Method for making asymmetric double-gate transistors Electricity 3 Active
US7361592B2 Method for producing a component comprising at least one germanium-based element and component obtained by such a method Electricity 3 Active
US9502292B2 Dual shallow trench isolation liner for preventing electrical shorts Electricity 2 Active
US9337350B2 Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same Electricity 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.