Adaptive clock duty-cycle controller
US11398812B1 · kind B1 · utility
2Cited by
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18Claims
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Key dates
| Filing date | Sep 25, 2021 |
| Grant date | Jul 26, 2022 |
| Priority date | — |
| Expiry date | Sep 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of measuring a clock signal includes launching an edge of a timing signal on a first edge of the clock signal, outputting an edge of a capture signal on a second edge of the clock signal, receiving the edge of the timing signal and the edge of the capture signal at a time-to-digital converter (TDC), and measuring a time delay using the TDC, wherein the time delay is between a time the edge of the timing signal is received at the TDC and a time the edge of the capture signal is received at the TDC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.