Droop detection and mitigation
US11402413B1 · kind B1 · utility
5Cited by
14References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2019 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Nov 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00346
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method includes filtering, with a low-pass filter, a voltage signal (Vdd) of a chip to create a filtered signal (Vref). The method further includes dividing Vref by a given factor. The method further includes determining whether a voltage droop occurred in Vdd by comparing Vdd to the divided Vref. The method further includes outputting a droop detection signal if Vdd is less than the divided Vref. In an embodiment, dividing Vref by the given factor includes selecting, with a multiplexer, one of a plurality of divided Vref signals outputted by a voltage divider. The selecting is based on a selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.