Memory system and operating method of the memory system
US11404097B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Aug 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.