Semiconductor structure and manufacturing method thereof
US11404328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Jul 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method includes: preparing a semiconductor substrate; sequentially forming an oxide layer and a sacrificial layer on the semiconductor substrate, the thickness of the oxide layer is a first thickness; forming a plurality of trenches in the semiconductor substrate, wherein the trenches extending from the sacrificial layer into the semiconductor substrate; forming an isolation dielectric layer on the plurality of trenches and the sacrificial layer, and removing the isolation dielectric layer on the sacrificial layer to form a plurality of isolation structures; forming a well region in the semiconductor substrate; processing the oxide layer by an etching process, so that the thickness of the oxide layer is equal to a second thickness, the first thickness is greater than the second thickness; and forming a polysilicon gate on the etched oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.