Semiconductor device with through-substrate via and its method of manufacture
US11404352B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Feb 15, 2019 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Mar 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dielectric layer is arranged on a main surface of a semiconductor substrate, a metal layer providing a contact area is embedded in the dielectric layer, a top metal is arranged on an opposite main surface of the substrate, and an electrically conductive interconnection through the substrate, which comprises a plurality of metallizations arranged in a plurality of via holes, connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer penetrating the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.