Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars
US11404390B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Oct 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81447
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.