Test key structure
US11404425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Jan 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a test key structure, the test key structure a substrate, a plurality of test key cells disposed on the substrate, wherein each test key cell includes a first gate structure arranged along a first direction (X-axis), a first diffusion region, a second diffusion region, a connection diffusion region and a share contact arranged along a second direction (Y-axis), wherein the first gate structure crosses over the first diffusion region to form a pull-up transistor (PU), the second gate structure crosses over the second diffusion region to form a pull-down transistor (PD), and wherein the plurality of share contacts and the plurality of connection diffusion regions of the plurality of test key cells are electrically connected to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.