Three-dimensional semiconductor memory device
US11404434B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Oct 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. Memory structures are disposed on the horizontal patterns. The memory structures include source structures and electrode structures. A division structure is disposed between adjacent horizontal patterns in the first direction and is configured to separate the source structures of adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns at a level lower than a level of the source structures. The etch stop pattern is connected to a lower portion of the division structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.