Patent · US Active

Memory device and fabrication method thereof

US11404438B2 · kind B2 · utility

1Cited by
2References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 4, 2020
Grant dateAug 2, 2022
Priority date
Expiry dateJan 23, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D62/115

Abstract

A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes array regions and a staircase region arranged between array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region and extending along the first lateral direction. The wall-structure regions of the first block and the second block are adjacent to each other and together form a wall structure in the staircase region. The memory device also includes a first separation structure, formed through the stack structure and positioned between the first block and the second block in array regions along the first lateral direction; and second dielectric layers positioned between the first block and the second block in the staircase region, and alternated with the first dielectric layers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.