Semiconductor device with air-void in spacer
US11404537B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Apr 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/679
Abstract
A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.