Inter-poly connection for parasitic capacitor and die size improvement
US11407636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2018 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Mar 14, 2039 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0792
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present disclosure, in some embodiments, relates to a method of forming a micro-electromechanical system (MEMS) package. The method includes forming one or more depressions within a capping substrate. A back-side of a MEMS substrate is bonded to the capping substrate after forming the one or more depressions, so that the one or more depressions define one or more cavities between the capping substrate and the MEMS substrate. A front-side of the MEMS substrate is selectively etched to form one or more trenches extending through the MEMS substrate, and one or more polysilicon vias are formed within the one or more trenches. A conductive bonding structure is formed on the front-side of the MEMS substrate at a location contacting the one or more polysilicon vias. The MEMS substrate is bonded to a CMOS substrate having one or more semiconductor devices by way of the conductive bonding structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.