Patent · US Active

Enlarged waveguide for photonic integrated circuit without impacting interconnect layers

US11409037B2 · kind B2 · utility

1Cited by
5References
20Claims
0Family size

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Key dates

Filing dateOct 28, 2020
Grant dateAug 9, 2022
Priority date—
Expiry dateOct 28, 2040

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG02B2006/1213
  • WIPO fieldOptics
  • WIPO sectorInstruments

Abstract

Structures and methods implement an enlarged waveguide. The structure may include a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a semiconductor substrate. An inter-level dielectric (ILD) layer is over the SOI substrate. A first waveguide has a lower surface extending at least partially into the buried insulator layer, which allows vertical enlargement of the waveguide, without increasing the thickness of the ILD layer or increasing the length of interconnects to other devices. The enlarged waveguide may include nitride, and can be implemented with other conventional silicon and nitride waveguides.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.