Inventor · Mechanicville, NY, US

Ryan Sporer

21Patents
3h-index
26Co-inventors
55Inventor score

Filing activity: May 11, 2016 → Oct 26, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US9806170B1 Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI Electricity 10 Active
US9634143B1 Methods of forming FinFET devices with substantially undoped channel regions Electricity 5 Active
US10043893B1 Post gate silicon germanium channel condensation and method for producing the same Electricity 5 Active
US10522655B2 Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI Electricity 2 Active
US9875936B1 Spacer defined fin growth and differential fin width Electricity 2 Active
US11650382B1 Optical components undercut by a sealed cavity Physics 1 Active
US10217660B2 Technique for patterning active regions of transistor elements in a late manufacturing stage Electricity 1 Active
US11409037B2 Enlarged waveguide for photonic integrated circuit without impacting interconnect layers Physics 1 Active
US12372717B2 Structure including hybrid plasmonic waveguide using metal silicide layer Physics 0 Active
US11907685B2 Structure and method for random code generation Electricity 0 Active
US11127843B2 Asymmetrical lateral heterojunction bipolar transistors Electricity 0 Active
US11094805B2 Lateral heterojunction bipolar transistors with asymmetric junctions Electricity 0 Active
US11569268B1 Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor Electricity 0 Active
US10326007B2 Post gate silicon germanium channel condensation and method for producing the same Electricity 0 Active
US12176351B2 Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor Electricity 0 Active
US11450573B2 Structure with different stress-inducing isolation dielectrics for different polarity FETs Electricity 0 Active
US10943814B1 Etch stop member in buried insulator of SOI substrate to reduce contact edge punch through Electricity 0 Active
US10056381B2 Punchthrough stop layers for fin-type field-effect transistors Electricity 0 Active
US11217678B2 Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI Electricity 0 Active
US11610843B2 Well tap for an integrated circuit product and methods of forming such a well tap Electricity 0 Active
US10050119B2 Method for late differential SOI thinning for improved FDSOI performance and HCI optimization Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.