Methods of hardware and software coordinated opt-in to advanced features on hetero ISA platforms
US11409572B2 · kind B2 · utility
1Cited by
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20Claims
0Family size
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Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Oct 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.