Integrated circuit (IC) power-up testing method and device, and electronic equipment
US11409623B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2021 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Apr 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) power-up testing method, an IC power-up testing device, a storage medium and an electronic equipment are disclosed. The IC power-up testing method includes: obtaining power-up testing parameters for an IC; obtaining a plurality of power-up testing waveforms; generating a plurality of power-up test instances by conducting parameter assignments for the power-up testing waveforms based on the power-up testing parameters; and performing power-up tests on the IC using the plurality of power-up test instances. The method allows simulating various IC power-up scenarios through a plurality of power-up test instances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.