Pin must-connects for improved performance
US11409935B2 · kind B2 · utility
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2References
11Claims
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Key dates
| Filing date | Dec 27, 2017 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | May 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/981
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a first metal level comprising a first plurality of interconnect lines along a first direction. A cell is on at least the first metal level, the cell having a pin comprising more than two of the first plurality of interconnect lines. A second metal level comprising a second plurality of interconnect lines overlays the first metal level, where the second plurality of interconnect lines is along a second direction. Two or more vias are on at least one of the second plurality of interconnect lines to connect to the pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.