Inventor · Beaverton, OR, US

Ranjith Kumar

17Patents
3h-index
44Co-inventors
52Inventor score

Filing activity: Jun 17, 2015 → Sep 22, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US10304946B2 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices Electricity 9 Active
US11139241B2 Integrated circuit device with crenellated metal trace layout Electricity 4 Active
US10523794B2 Method and apparatus for managing multipath transmission control protocol Electricity 3 Active
US11068640B2 Power shared cell architecture Electricity 1 Active
US11271010B2 Multi version library cell handling and integrated circuit structures fabricated therefrom Electricity 1 Active
US10203882B2 Method for managing multiple bandwidth boost solutions co-existing in an electronic device Emerging Cross-Sectional Technologies 1 Active
US11153779B2 Apparatus and method for transmitting and receiving data based on an identified event in wireless communication system Electricity 0 Active
US11409935B2 Pin must-connects for improved performance Electricity 0 Active
US12223247B2 Logic cell structures and related methods Physics 0 Active
US11816412B2 Logic cell structures and related methods Physics 0 Active
US10847635B2 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices Electricity 0 Active
US12310044B2 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices Electricity 0 Active
US11764219B2 Metal space centered standard cell architecture to enable higher cell density Electricity 0 Active
US11522072B2 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices Electricity 0 Active
US11682664B2 Standard cell architecture with power tracks completely inside a cell Electricity 0 Active
US12067338B2 Multi version library cell handling and integrated circuit structures fabricated therefrom Electricity 0 Active
US11996362B2 Integrated circuit device with crenellated metal trace layout Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.