Multi-fuse memory cell circuit and method
US11410740B2 · kind B2 · utility
2Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2021 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Jul 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.