Three-dimensional semiconductor memory device
US11410951B2 · kind B2 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2021 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Mar 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.