Hybrid bonding technology for stacking integrated circuits
US11410972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2020 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Oct 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.