Field plate and isolation structure for high voltage device
US11411086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2020 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Sep 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated chip includes a field plate overlying an isolation structure. A gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an upper surface of the gate electrode to a front-side of the substrate. The etch stop layer overlies a drift region disposed between the source region and the drain region. The field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front-side of the substrate to a point below the front-side of the substrate. The isolation structure is disposed laterally between the gate electrode and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.