Memory device and operation method thereof
US11417390B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 7, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Jul 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and an operation method thereof are provided. The memory device includes an input/output data latch circuit and a bit line sensing amplifier circuit. The input/output data latch circuit is coupled between a main input/output line pair and a local input/output line pair. The local input/output line pair is coupled to a plurality of bit line pairs through the bit line sensing amplifier circuit. The memory device performs a two-stage operation to input or output data of a selected bit line pair among the bit line pairs. The selected bit line pair connects to the local input/output line pair only during one stage operation of the two-stage operation. Further, during the other stage operation of the two-stage operation, the data of the selected bit line pair latched in the input/output data latch circuit is transmitted to the main input/output line pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.