Conductive cap-based approaches for conductive via fabrication and structures resulting therefrom

US11417567B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Florian Gstrein · Portland, US
• Eungnak Han · Portland, US
• Rami Hourani · Santa Clara, US
• Ruth A. Brain · Portland, US
• Paul A. Nyhus · Portland, US
• Manish Chandhok · Beaverton, US
• Charles H. Wallace · Portland, US
• Chi-Hwa Tsang · Beaverton, US

Key dates

• Filing date: Dec 23, 2016
• Grant date: Aug 16, 2022
• Expiry date: Dec 23, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76883
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.