NPN heterojunction bipolar transistor in CMOS flow
US11417646B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Jun 3, 2016 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Jun 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.