Inventor · Sachse, TX, US

Deborah J. Riley

24Patents
5h-index
31Co-inventors
69Inventor score

Filing activity: Jan 21, 2000 → Mar 14, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US7098099B1 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof Electricity 12 Expired
US6492275B2 Control of transistor performance through adjustment of spacer oxide profile with a wet etch Electricity 8 Expired
US8877581B2 Strain-engineered MOSFETs having rimmed source-drain recesses Electricity 6 Active
US7537988B2 Differential offset spacer Electricity 6 Active
US8927385B2 ZTCR poly resistor in replacement gate flow Electricity 5 Active
US7732284B1 Post high-k dielectric/metal gate clean Emerging Cross-Sectional Technologies 5 Active
US8043921B2 Nitride removal while protecting semiconductor surfaces for forming shallow junctions Electricity 4 Active
US8691644B2 Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor Electricity 3 Active
US9093555B2 Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved EPI profile Electricity 3 Active
US7371691B2 Silicon recess improvement through improved post implant resist removal and cleans Electricity 2 Expired
US8470707B2 Silicide method Electricity 2 Active
US7323403B2 Multi-step process for patterning a metal gate electrode Electricity 2 Expired
US7384869B2 Protection of silicon from phosphoric acid using thick chemical oxide Electricity 2 Expired
US7569464B2 Method for manufacturing a semiconductor device having improved across chip implant uniformity Electricity 1 Active
US9263444B2 Devices having inhomogeneous silicide schottky barrier contacts Electricity 1 Active
US9385117B2 NPN heterojunction bipolar transistor in CMOS flow Electricity 1 Active
US7132365B2 Treatment of silicon prior to nickel silicide formation Electricity 1 Expired
US10026837B2 Embedded SiGe process for multi-threshold PMOS transistors Electricity 1 Active
US9659825B2 Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile Electricity 0 Active
US7422969B2 Multi-step process for patterning a metal gate electrode Electricity 0 Active
US11004612B2 Low temperature sub-nanometer periodic stack dielectrics Electricity 0 Active
US9780001B2 Devices having inhomogeneous silicide schottky barrier contacts Electricity 0 Active
US11417646B2 NPN heterojunction bipolar transistor in CMOS flow Electricity 0 Active
US9224656B2 Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved gate spacer control Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.