Memory cell and fabricating method of the same
US11417742B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2021 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Mar 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.