Semiconductor arrangement with airgap and method of forming
US11417749B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2019 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Jun 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/792
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor arrangement includes a gate structure disposed between a first source/drain region and a second source/drain region and a first contact disposed over the first source/drain region. The semiconductor arrangement includes a second contact disposed over the second source/drain region and an airgap disposed between the first contact and the second contact and over the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.