System and method for synthesis of a network-on-chip to determine optimal path with load balancing
US11418448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Apr 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system, and corresponding method, is described for finding the optimal or the best set of routes from a master to each of its connected slaves, for all the masters and slaves using a Network-on-Chip (NoC). More precisely, some embodiments of the invention apply to a class of NoCs that utilize a two-dimensional mesh topology, wherein a set of switches are arranged on a two-dimensional grid. Masters (initiators or sources) inject data packets or traffic into the NoC. Slaves (targets or destinations) service the data packets or traffic traveling through the NoC. The NoC includes switches and links. Additionally, the optimal routes defined by the system includes moving the traffic in a way that avoids deadlock scenarios.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.