Iterative estimation hardware
US11422802B2 · kind B2 · utility
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Key dates
| Filing date | Dec 23, 2019 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Mar 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5521
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.