Patent · US Active

Restartable cache write-back and invalidation

US11422811B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Gideon Gerzon · Jerusalem, IL
Dror Caspi · Kiryat Yam, IL
Arie Aharon · Haifa, IL
Ido Ouziel · Atlit, IL

Key dates

Filing date	Nov 13, 2020
Grant date	Aug 23, 2022
Priority date	—
Expiry date	Nov 13, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/683
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor includes a global register to store a value of an interrupted block count. A processor core, communicably coupled to the global register, may, upon execution of an instruction to flush blocks of a cache that are associated with a security domain: flush the blocks of the cache sequentially according to a flush loop of the cache; and in response to detection of a system interrupt: store a value of a current cache block count to the global register as the interrupted block count; and stop execution of the instruction to pause the flush of the blocks of the cache. After handling of the interrupt, the instruction may be called again to restart the flush of the cache.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.