Decoding system and physical layout for analog neural memory in deep learning artificial neural network

US11423979B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Hieu Van Tran · San Jose, US
• Thuan Vu · San Jose, US
• Stanley Hong · Palo Alto, US
• Stephen Trinh · San Jose, US
• Anh Ly · San Jose, US
• Han Tran · Beaverton, US
• Kha Nguyen · Mission Viejo, US
• Hien Pham · Ngọc Lặc, VN

Key dates

• Filing date: Jul 3, 2019
• Grant date: Aug 23, 2022
• Expiry date: Jul 3, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/044
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.