Memory circuits and related methods
US11424233B1 · kind B1 · utility
2Cited by
0References
20Claims
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Assignee
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Key dates
| Filing date | Apr 8, 2021 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Apr 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided. The method includes providing a first die and a second die. The first die may include a memory array that includes a plurality of memory cells and a sensing element. The second die may include an address decoder associated with the memory array of the first die. The method also includes coupling the second die to the sensing element of the first die, and providing an encapsulant at least partially encapsulating the first die and the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.