Small-area and low-voltage anti-fuse element and array
US11424252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2020 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Jan 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.